By Libin Yao
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Extra info for Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS (The Springer International Series in Engineering and Computer Science)
The DR is the ratio between the maximum input signal power can be applied to the input of the converter without signiﬁcant performance degradation, and the minimum detectable input signal power. A signiﬁcant performance degradation of a converter is considered as the SNR drops more than 3 dB below the peak SNR value. The minimum detectable input signal is the input power that the converter has for a SNR of 0 dB. • Overload Level. The OL is the relative input amplitude where the SNR decreases by 3 dB below the peak SNR.
4 ADCs in Nanometer CMOS As a major building block, the ADC is widely used in mixed-signal designs. As an interface between the analog world to the digital world, ADCs are implemented with the same technology as the digital circuit. Hence the power supply voltage reduction is inevitable. Fig. 6 shows the Nyquist ADC paper numbers published in ISSCC and the CMOS technologies used in recent years. It is clearly seen that most of the ADC designs are made in nanometer CMOS technologies. The decrease of the supply voltage obviously results into analog circuit performance degradation.
The quantizer can be modeled as a quantization noise source, shown in Fig. 8. 4) where es2 is the maximum input signal power. 4) gives the best possible SNR for a N-bit ADC. 3 Oversampling and Noise Shaping In the previous section, the quantization noise is introduced. It is assumed that the quantization noise is independent from the input signal. e. the quantization noise is the so-called white noise. Shown in Fig. 9, the power spectral density of the quantization noise, Se ( f ) is white and all its power is within 2 ± f s /2, where f s is the sampling frequency.
Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS (The Springer International Series in Engineering and Computer Science) by Libin Yao